1. Field of the Invention
The present invention relates to a semiconductor device. More particularly, the invention relates to a technique applied to a power MOS transistor having a high breakdown voltage.
2. Description of the Related Art
Hitherto known is a power IC comprising a semiconductor device having a high breakdown voltage and a semiconductor device having a low breakdown voltage, both provided on the same substrate. The power IC further comprises a power MOS transistor at the output stage. The power MOS transistor needs to have both a high breakdown voltage and a low on-resistance.
A conventional power MOS transistor will be described, with reference to FIGS. 1A and 1B. FIG. 1A is a plan view of the MOS transistor, which is an LDMOS (Lateral Double-Diffused MOS) transistor. FIG. 1B is a sectional view taken along line 1B—1B shown in FIG. 1A.
As FIGS. 1A and 1B show, an n−-type epitaxial silicon layer 11 is provided in a surface of a p-type silicon substrate 10. An n+-type buried layer 12 is provided in the junction between the substrate 10 and the layer 11. Body regions 13 (p-type impurity-diffused layers), which are shaped like a strip, are provided in the surface of the epitaxial silicon layer 11. In each body region 13, a source region 14 (n+-type impurity-diffused layer) and a contact region 15 (p+-type impurity-diffused layer) are provided. A drain region 16 (n+-type impurity-diffused layer) and an offset region 17 (n−-type impurity-diffused layer) are provided in the surface of the epitaxial silicon layer 11. The drain region 16 surrounds the body region 13. The offset region 17 surrounds the drain region 16. In the epitaxial silicon layer 11, sinker layers 18 extend downwards, from the surface of the layer 11 to the buried layer 12. On the silicon layer 11 there are provided gate insulating films 19 and LOCOS (LOCal Oxidation of Silicon) insulating films 20. Each gate insulating film 19 lies on the body region 13 and is connected to the adjacent LOCOS insulating film 20, which reaches a drain region 16. Gate electrodes 21 are provided, each partly on a gate insulating film 19 and partly on the LOCOS insulating film 20 connected to the film 19. Each gate electrode 21 surrounds one body region 13. Drain electrodes 22 lie on the drain regions 16. Source electrodes 23 are provided, each on one source region 14 and one contact region 15. Thus, LDMOS transistors have been formed.
FIG. 2A is a sectional view of another conventional LDMOS transistor.
As is illustrated in FIG. 2A, a p-type well region 25 is provided in one surface of a silicon substrate 10. A source region 14 (n+-type impurity-diffused layer) and an offset region 17 (n−-type impurity-diffused layer) are provided in the surface of the well region 25 and spaced apart from each other. A contact region 15 (p+-type impurity-diffused layer) is provided in the surface of the well region 25 and contacts the source region 14. A drain region 16 (n+-type impurity-diffused layer) is provided in the surface of the offset region 17 and isolated from the well region 25. A gate insulating film 19 lies on the well region 25 and extends from the source region 14 to the offset region 17. A gate electrode 21 is provided on the gate insulating film 19. An inter-layer insulating film 26 lies on the well region 25 and covers the gate electrode 21. A gate electrode 22 and a drain electrode 23 are provided in the inter-layer insulating film 26. Thus, an LDMOS transistor has been formed.
FIG. 2B represents the impurity-concentration profile in the plane taken along line 2B—2B shown in FIG. 2A. In FIG. 2B, the impurity concentration is plotted on the ordinate, and the depth, measured from the drain region 16, is plotted on the abscissa.
As seen from FIG. 2B, the drain region 16 is about 0.12 μm deep from its upper surface. The offset region 17 is about 0.13 μm deep from the upper surface of the drain region 16. Namely, the offset region 17 is formed to a depth slightly greater than the depth to which the drain region 16 is formed, in the conventional power MOS transistor.